Freescale Semiconductor /MKL28T7_CORE1 /LPI2C0 /MTDR

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Interpret as MTDR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DATA0 (000)CMD

CMD=000

Description

Master Transmit Data Register

Fields

DATA

Transmit Data

CMD

Command Data

0 (000): Transmit DATA[7:0].

1 (001): Receive (DATA[7:0] + 1) bytes.

2 (010): Generate STOP condition.

3 (011): Receive and discard (DATA[7:0] + 1) bytes.

4 (100): Generate (repeated) START and transmit address in DATA[7:0].

5 (101): Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.

6 (110): Generate (repeated) START and transmit address in DATA[7:0] using high speed mode.

7 (111): Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.

Links

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